View CS4340-BS_1025572.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs4340 24-bit, 96 khz stereo dac for audio features l complete stereo dac system: interpolation, d/a, output analog filtering l 101 db dynamic range l 91 db thd+n l low clock jitter sensitivity l +3 v to +5 v power supply l filtered line level outputs l on-chip digital de-emphasis for 32, 44.1, and 48 khz l 30 mw with 3 v supply l popguard ? technology for control of clicks and pops description the cs4340 is a complete stereo digital-to-analog sys- tem including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis and switched capacitor analog filtering. the advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. the cs4340 accepts data at audio sample rates from 2 khz to 100 khz, consumes very little power, and oper- ates over a wide power supply range. the features of the cs4340 are ideal for dvd players, cd players, set-top box and automotive systems. ordering information cs4340-ks 16-pin soic, -10 to 70 c CS4340-BS 16-pin soic, -40 to 85 c cdb4340 evaluation board i ds dac analog filter serial input interface interpolation filter analog filter mutec aoutl aoutr rst lrck sdata mclk ds external mute control sclk/dem1 dac interpolation filter de-emphasis dem0 dif0 dif1 nov 00 ds297pp3
cs4340 2 ds297pp3 table of content 1. characteristics and specifications .............................................. 5 analog characteristics................................................................... 5 analog characteristics................................................................... 6 analog characteristics................................................................... 7 power and thermal characteristics ......................................... 8 digital characteristics.................................................................... 8 recommended operating conditions .......................................... 9 switching characteristics ........................................................... 10 2. typical connection diagram ............................................................ 12 3. pin description ....................................................................................... 13 4. applications ............................................................................................ 16 4.1 grounding and power supply decoupling ......................................... 16 4.2 oversampling modes ......................................................................... 16 4.3 recommended power-up sequence ................................................. 16 4.4 popguard ? transient control ............................................................ 16 5. interpolation filter response plots .............................. 17 6. digital interface formats ............................................. 19 7. analog performance plots ............................................................. 21 8. parameter definitions ........................................................................ 26 total harmonic distortion + noise (thd+n) ............................................. 26 dynamic range ......................................................................................... 26 interchannel isolation................................................................................. 26 interchannel gain mismatch ...................................................................... 26 gain error .................................................................................................. 26 gain drift.................................................................................................... 26 9. references .............................................................................................. 26 10. package dimensions ........................................................................... 27 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
cs4340 ds297pp3 3 list of figures figure 1. external serial mode input timing ............................................................. 11 figure 2. internal serial mode input timing .............................................................. 11 figure 3. internal serial clock generation ................................................................ 11 figure 4. typical connection diagram ...................................................................... 12 figure 5. base-rate stopband rejection .................................................................. 17 figure 6. base-rate transition band ........................................................................ 17 figure 7. base-rate transition band (detail)............................................................ 17 figure 8. base-rate passband ripple ...................................................................... 17 figure 9. high-rate stopband rejection ................................................................... 17 figure 10. high-rate transition band ....................................................................... 17 figure 11. high-rate transition band (detail) .......................................................... 18 figure 12. high-rate passband ripple ..................................................................... 18 figure 13. output test load...................................................................................... 18 figure 14. maximum loading .................................................................................... 18 figure 15. power vs. sample rate (va = 5v) ........................................................... 18 figure 16. cs4340 format 0 (i 2 s)............................................................................. 19 figure 17. cs4340 format 1 ..................................................................................... 19 figure 18. cs4340 format 2 ..................................................................................... 20 figure 19. cs4340 format 3 ..................................................................................... 20 figure 20. de-emphasis curve ................................................................................. 21 figure 21. fft 0 db input, brm, va = 3v ................................................................ 22 figure 22. fft -60 db input, brm, va = 3v ............................................................. 22 figure 23. fft idle noise, brm, va = 3v................................................................. 22 figure 24. fade-to-noise linearity, brm, va = 3v................................................... 22 figure 25. thdn vs ampl, brm, va = 3v ................................................................ 22 figure 26. thdn vs freq, brm, va = 3v ................................................................. 22 figure 27. fft 0 db input, brm, va = 5v ................................................................ 23 figure 28. fft -60 db input, brm, va = 5v ............................................................. 23 figure 29. fft idle noise, brm, va = 5v................................................................. 23 figure 30. fade-to-noise linearity, brm, va = 5v................................................... 23 figure 31. thdn vs ampl, brm, va = 5v ................................................................ 23 figure 32. thdn vs freq, brm, va = 5v ................................................................. 23 figure 33. fft 0 db input, hrm, va = 3v ................................................................ 24 figure 34. fft -60 db input, hrm, va = 3v ............................................................. 24 figure 35. fft idle noise, hrm, va = 3v ................................................................ 24 figure 36. fade-to-noise linearity, hrm, va = 3v................................................... 24 figure 37. thdn vs ampl, hrm, va = 3v ................................................................ 24 figure 38. thdn vs freq, hrm, va = 3v ................................................................. 24 figure 39. fft 0 db input, hrm, va = 5v ................................................................ 25 figure 40. fft -60 db input, hrm, va = 5v ............................................................. 25 figure 41. fft idle noise, hrm, va = 5v ................................................................ 25 figure 42. fade-to-noise linearity, hrm, va = 5v................................................... 25 figure 43. thdn vs ampl, hrm, va = 5v ................................................................ 25 figure 44. thdn vs freq, hrm, va = 5v ................................................................. 25
cs4340 4 ds297pp3 list of tables table 1. internal serial clock mode .......................................................................... 14 table 2. external serial clock mode ......................................................................... 14 table 3. common master clock frequencies ........................................................... 14 table 4. digital interface format - dif1 and dif0 ................................................... 15
cs4340 ds297pp3 5 1. characteristics and specifications analog characteristics (test conditions (unless otherwise specified): t a = 25 c; logic "1" = va = 5 v; logic "0" = agnd;full-scale output sine wave, 997 hz; mclk = 12.288 mhz; fs for base-rate mode = 48 khz, sclk = 3.072 mhz, measurement bandwidth 10 hz to 20 khz, unless otherwise specified; fs for high- rate mode = 96 khz, sclk = 6.144 mhz, measurement bandwidth 10 hz to 40 khz, unless otherwise specified. test load r l = 10 k w , c l = 10 pf (see figure 13) notes: 1. cs4340-ks parts are tested at 25 c and min/max performance numbers are guaranteed across the specified temperature range, t a . 2. one-half lsb of triangular pdf dither is added to data. parameter base-rate mode high-rate mode symbol min typ max min typ max unit cs4340-ks dynamic performance for va = 5 v (note 1) specified temperature range t a -10 - 70 -10 - 70 c dynamic range (note 2) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted 93 96 - - 98 101 95 97 - - - - 91 95 - - 96 100 94 97 - - - - db db db db total harmonic distortion + noise (note 2) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -91 -78 -38 -90 -75 -35 -86 - - - - - - - - - - - -89 -76 -36 -89 -74 -34 -84 - - - - - db db db db db db interchannel isolation (1 khz) - 102 - - 102 - db cs4340-ks dynamic performance for va = 3 v (note 1) specified temperature range t a -10 - 70 -10 - 70 c dynamic range (note 2) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted 89 92 - - 94 97 93 96 - - - - 87 91 - - 92 96 92 96 - - - - db db db db total harmonic distortion + noise (note 2) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -94 -74 -34 -93 -73 -33 -88 - - - - - - - - - - - -92 -72 -32 -91 -72 -32 -87 - - - - - db db db db db db interchannel isolation (1 khz) - 102 - - 102 - db
cs4340 6 ds297pp3 analog characteristics (continued) notes: 3. CS4340-BS parts are tested at the extremes of the specified temperature range and min/max performance numbers are guaranteed across the specified temperature range, t a . typical numbers are taken at 25 c. parameter base-rate mode high-rate mode symbol min typ max min typ max unit CS4340-BS dynamic performance for va = 5 v (note 3) specified temperature range t a -40 - 85 -40 - 85 c dynamic range (note 2) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted tbd tbd - - 98 101 95 97 - - - - tbd tbd - - 96 100 94 97 - - - - db db db db total harmonic distortion + noise (note 2) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -91 -78 -38 -90 -75 -35 tbd - - - - - - - - - - - -89 -76 -36 -89 -74 -34 tbd - - - - - db db db db db db interchannel isolation (1 khz) - 102 - - 102 - db CS4340-BS dynamic performance for va = 3 v (note 3) specified temperature range t a -40 - 85 -40 - 85 c dynamic range (note 2) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted tbd tbd - - 94 97 93 96 - - - - tbd tbd - - 92 96 92 96 - - - - db db db db total harmonic distortion + noise (note 2) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -94 -74 -34 -93 -73 -33 tbd - - - - - - - - - - - -92 -72 -32 -91 -72 -32 tbd - - - - - db db db db db db interchannel isolation (1 khz) - 102 - - 102 - db
cs4340 ds297pp3 7 analog characteristics (continued) notes: 4. refer to figure 14. 5. filter response is guaranteed by design. 6. response is clock dependent and will scale with fs. note that the response plots (figures 5-12) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 7. for base-rate mode, the measurement bandwidth is 0.5465 fs to 3 fs. for high-rate mode, the measurement bandwidth is 0.577 fs to 1.4 fs. 8. de-emphasis is not available in high-rate mode. parameters symbol min typ max units analog output full scale output voltage 0.63?va 0.7?va 0.77?va vpp quiescent voltage v q -0.5?va- vdc interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c ac-load resistance (note 4) r l 3- -k w load capacitance (note 4) c l --100pf parameter base-rate mode high-rate mode symbol min typ max min typ max unit combined digital and on-chip analog filter response (note 5) passband (note 6) to -0.05 db corner to -0.1 db corner to -3 db corner 0 - 0 - - - .4535 - .4998 - 0 0 - - - - .4621 .4982 fs fs fs frequency response 10 hz to 20 khz -.02 - +.08 -0.06 - 0.2 db stopband .5465 - - .577 - - fs stopband attenuation (note 7) 50 - - 55 - - db group delay tgd - 9/fs - - 4/fs - s passband group delay deviation 0 - 40 khz 0 - 20 khz - - - 0.36/fs - - - - 1.39/fs 0.23/fs - - s s de-emphasis error fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - +.2/-.1 +.05/-.14 +0/-.22 (note 8) db db db
cs4340 8 ds297pp3 power and thermal characteristics notes: 9. refer to figure 15. 10. valid with the recommended capacitor values on filt+ and vq as shown in figure 4. increasing the capacitance will also increase the psrr. digital characteristics (for -ks parts t a = -10 to 70 c; for -bs parts t a = -40 to 85c; va = 2.7 v - 5.5 v) cs4340-ks CS4340-BS parameters symbol min typ max min typ max units power supplies power supply current normal operation va = 5 v power-down state i a i a - - 15 60 18 - - - 15 60 tbd - ma m a power dissipation (note 9) va = 5 v normal operation power-down - - 75 0.3 90 - - - 75 0.3 tbd - mw mw power supply current normal operation va = 3 v power-down state i a i a - - 10 30 14 - - - 10 30 tbd - ma m a power dissipation (note 9) va = 3 v normal operation power-down - - 30 0.09 42 - - - 30 0.09 tbd - mw mw package thermal resistance q ja - 110 - - 110 - c/watt power supply rejection ratio (1 khz) (note 10) (60 hz) psrr - - 60 40 - - - - 60 40 - - db db parameters symbol min typ max units high-level input voltage va = 5 v va = 3 v v ih 2.0 2.0 - - - - v v low-level input voltage va = 5 v va = 3 v v il - - - - 0.8 0.8 v v input leakage current i in --10 m a input capacitance - 8 - pf maximum mutec drive current - 3 - ma
cs4340 ds297pp3 9 absolute maximum ratings (agnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd = 0v; all voltages with respect to ground.) parameters symbol min max units dc power supply va -0.3 6.0 v input current, any pin except supplies i in - 10 ma digital input voltage v ind -0.3 va+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units dc power supply va 2.7 5.0 5.5 v
cs4340 10 ds297pp3 switching characteristics (va = 2.7 v - 5.5 v; inputs: logic 0 = 0 v, logic 1 = va, cl = 20 pf; for -ks parts t a = -10 to 70 c; for -bs parts t a = -40 to 85c) notes: 11. in internal sclk mode, the duty cycle must be 50% +/- 1/2 mclk period. 12. the sclk / lrck ratio may be either 32, 48, or 64. this ratio depends on part type and mclk/lrck ratio. (see figures 16-19) parameters symbol min typ max units input sample rate base-rate mode high-rate mode fs 2 50 - - 50 100 khz khz mclk pulse width high mclk/lrck = 512 10 - 1000 ns mclk pulse width low mclk/lrck = 512 10 - 1000 ns mclk pulse width high mclk / lrck = 384 or 192 21 - 1000 ns mclk pulse width low mclk / lrck = 384 or 192 21 - 1000 ns mclk pulse width high mclk / lrck = 256 or 128 31 - 1000 ns mclk pulse width low mclk / lrck = 256 or 128 31 - 1000 ns external sclk mode lrck duty cycle (external sclk only) 40 50 60 % sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk period mclk / lrck = 512, 256 or 384 t sclkw -- ns sclk period mclk / lrck = 128 or 192 t sclkw -- ns sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdata valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdata hold time t sdh 20 - - ns internal sclk mode lrck duty cycle (internal sclk only) (note 11) - 50 - % sclk period (note 12) t sclkw -- ns sclk rising to lrck edge t sclkr -- m s sdata valid to sclk rising setup time t sdlrs -- ns sclk rising to sdata hold time mclk / lrck = 512, 256 or 128 t sdh -- ns sclk rising to sdata hold time mclk / lrck = 384 or 192 t sdh -- ns 1 128 () fs --------------------- - 1 64 () fs ------------------ 1 sclk ---------------- tsclkw 2 ----------------- - 1 512 () fs --------------------- -10 + 1 512 () fs --------------------- -15 + 1 384 () fs --------------------- -15 +
cs4340 ds297pp3 11 sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 1. external serial mode input timing sdata *internal sclk lrck sclkw t sdlrs t sdh t sclkr t figure 2. internal serial mode input timing *the sclk pulses shown are internal to the cs4340. sdata lrck mclk *internal sclk 1 n 2 n figure 3. internal serial clock generation * the sclk pulses shown are internal to the cs4340. n equals mclk divided by sclk
cs4340 12 ds297pp3 2. typical connection diagram 13 audio data processor external clock mclk agnd aoutr cs4340 sdata lrck va aoutl 3 4 5 14 0.1 f + 1f 12 +5vto+3v 3.3 f 3.3 f 10 k w c c 560 w 560 w + + mode configuration 8 6 7 sclk/dem1 1 2 dif1 dif0 dem0 rst mutec 16 optional mute circuit 15 1f 0.1 f audio output audio output r l + 560 c= 4 p f s r l 560 r l r l + + 10 k w .1 f 1f 9 10 11 ref_gnd filt+ vq left right figure 4. typical connection diagram
cs4340 ds297pp3 13 3. pin description rst 1 reset ( input ) - the device enters a low power mode and all internal state machines are reset to the default settings when low. rst should be held low during power-up until the power supply, master and left/right clocks are stable. sdata 2 serial audio data ( input ) - two's complement msb-first serial data is input on this pin. the data is clocked into sdata via the serial clock and the channel is determined by the left/right clock. the required relationship between the left/right clock, serial clock and serial data is defined by the dif1-0 pins. the options are detailed in figures 16-19. sclk 3 serial clock ( input ) - clocks the individual bits of the serial data into the sdata pin. the required relationship between the left/right clock, serial clock and serial data is defined by the dif1-0 pins. the options are detailed in figures 16-19. the cs4340 supports both internal and external serial clock generation modes. internal sclk mode is used to gain access to extra de-emphasis modes. internal serial clock mode - in the internal serial clock mode, the serial clock is internally derived and synchronous with the master clock and left/right clock. the sclk/lrck frequency ratio is either 32, 48, or 64 depending upon the dif1-0 pins as shown in figures 16-19. opera- tion in this mode is identical to operation with an external serial clock synchronized with lrck. external serial clock mode - the cs4340 will enter the external serial clock mode whenever 16 low to high transitions are detected on the sclk pin during any phase of the lrck period. the device will revert to internal serial clock mode if no low to high transitions are detected on the sclk pin for 2 consecutive periods of lrck. 15 2 14 3 13 4 16 1 11 6 10 7 9 8 12 5 reset rst mutec mute control serial data sdata aoutl left analog output serial clock / de-emphasis sclk / dem1 va analog power left/right clock lrck agnd analog ground master clock mclk aoutr right analog output digital interface format dif1 ref_gnd reference ground digital interface format dif0 vq quiescent voltage de-emphasis dem0 filt+ positive voltage reference
cs4340 14 ds297pp3 dem1 and dem0 3 & 8 de-emphasis control ( input ) - implementation of the standard 15 m s/50 m s digital de-emphasis filter response, figure 20, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 khz sample rates. when using internal serial clock mode, as described above, pin 3 is available for de-emphasis control, dem1, and all de-emphasis filters are available, table 3. when using external serial clock mode, as described above, pin 3 is not available for de-emphasis use and only the 44.1 khz de-emphasis filter is available, table 4. note: de-emphasis is not available in high-rate mode. lrck 4 left/right clock ( input ) - the left/right clock determines which channel is currently being input on the serial audio data input, sdata. the frequency of the left/right clock must be at the input sample rate. audio samples in left/right sample pairs will be simultaneously output from the digital-to-analog converter whereas right/left pairs will exhibit a one sample period difference. the required relationship between the left/right clock, serial clock and serial data is defined by the dif1-0 pins. the options are detailed in figures 16-19. mclk 5 master clock ( input ) - the master clock frequency must be either 256x, 384x or 512x the input sample rate in base rate mode (brm) and either 128x or 192x the input sample rate in high rate mode (hrm). table 3 illustrates several standard audio sample rates and the required master clock frequencies. dem1 demo description 00disabled 0144.1khz 1048khz 1132khz table 1. internal serial clock mode demo description 0 disabled 1 44.1khz table 2. external serial clock mode sample rate (khz) mclk (mhz) hrm brm 128x 192x 256x 384x 512x 32 4.0960 6.1440 8.1920 12.2880 16.3840 44.1 5.6448 8.4672 11.2896 16.9344 22.5792 48 6.1440 9.2160 12.2880 18.4320 24.5760 64 8.1920 12.2880 - - - 88.2 11.2896 16.9344 - - - 96 12.2880 18.4320 - - - table 3. common master clock frequencies
cs4340 ds297pp3 15 dif1 and dif0 6 & 7 digital interface format (i nput ) - the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 16-19 filt+ 9 positive voltage reference ( output ) - positive reference for internal sampling circuits. an external capacitor is required from filt+ to analog ground, as shown in figure 4. the recom- mended value will typically provide 60 db of psrr at 1 khz and 40 db of psrr at 60 hz. filt+ is not intended to supply external current. filt+ has a typical source impedance of 250 k w and any current drawn from this pin will alter device performance. vq 10 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage, typi- cally 50% of va. capacitors must be connected from vq to analog ground, as shown in figure 4. vq is not intended to supply external current. vq has a typical source impedence of 250 k w and any current drawn from this pin will alter device performance. ref_gnd 11 reference ground ( input ) - ground reference for the internal sampling circuits. must be con- nected to analog ground. aoutr and aoutl 12 & 15 analog outputs ( output ) - the full scale analog output level is specified in the analog charac- teristics specifications table. agnd 13 ground ( input ) - ground reference. va 14 analog power ( input ) - analog power supply. typically 3 to 5 vdc. mutec 16 mute control ( output ) - the mute control pin goes high during power-up initialization, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. this pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. use of mute control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. . dif1 dif0 description format figure 00i 2 s, up to 24-bit data 0 16 0 1 left justified, up to 24-bit data 1 17 1 0 right justified, 24-bit data 2 18 1 1 right justified, 16-bit data 3 19 table 4. digital interface format - dif1 and dif0
cs4340 16 ds297pp3 4. applications 4.1 grounding and power supply decoupling as with any high resolution converter, the cs4340 requires careful attention to power supply and grounding arrangements to optimize performance. figure 4 shows the recommended power arrange- ment with va connected to a clean supply. decou- pling capacitors should be located as close to the device package as possible. 4.2 oversampling modes the cs4340 operates in one of two oversampling modes. base rate mode supports input sample rates up to 50 khz while high rate mode supports input sample rates up to 100 khz. the devices op- erate in base rate mode (brm) when mclk/lrck is 256, 384 or 512 and in high rate mode (hrm) when mclk/lrck is 128 or 192. 4.3 recommended power-up sequence rst should be held low until the power supply, master and left/right clocks are stable. 4.4 popguard ? transient control the cs4340 uses popguard ? technology to mini- mize the effects of output transients during power- up and power-down. this technique, when used with external dc-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. when the device is initially powered-up, the audio outputs, aoutl and aoutr, are clamped to agnd. following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. approximately 10,000 left/right clock cycles later, the outputs reach v q and audio output begins. this gradual voltage ramping allows time for the external dc-blocking capacitor to charge to the quiescent voltage, mini- mizing the power-up transient. to prevent transients at power-down, the device must first enter its power-down state by setting the rst pin low. when this occurs, audio output ceas- es and the internal output buffers are disconnected from aoutl and aoutr. in their place, a soft- start current sink is substituted which allows the dc-blocking capacitors to slowly discharge. once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. to prevent an audio transient at the next power-on, it is necessary to ensure that the dc-blocking ca- pacitors have fully discharged before turning off the power or exiting the power-down state. if not, a transient will occur when the audio outputs are ini- tially clamped to agnd. the time that the device must remain in the power-down state is related to the value of the dc-blocking capacitance. for ex- ample, with a 3.3 f capacitor, the minimum pow- er-down time will be approximately 0.4 seconds. use of the mute control function is recommended for designs requiring the absolute minimum in ex- traneous clicks and pops. also, use of the mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. see the cdb4340/41 data sheet for a suggested mute circuit.
cs4340 ds297pp3 17 5. interpolation filter response plots figure 5. base-rate stopband rejection figure 6. base-rate transition band figure 7. base-rate transition band (detail) figure 8. base-rate passband ripple figure 9. high-rate stopband rejection figure 10. high-rate transition band
cs4340 18 ds297pp3 figure 11. high-rate transition band (detail) figure 12. high-rate passband ripple aoutx agnd 3.3 f v out r l c l + figure 13. output test load 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k w ) l 125 3 20 figure 14. maximum loading 75 50 30 power (mw) sample rate (khz) b r m h r m 70 65 60 55 40 50 60 70 80 90 100 figure 15. power vs. sample rate (va = 5v)
cs4340 ds297pp3 19 6. digital interface formats lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode i 2 s, 16-bit data and int sclk = 32 fs if mclk/lrck = 512, 256 or 128 i 2 s, up to 24-bit data and int sclk = 48 fs if mclk/lrck = 384 or 192 i 2 s, up to 24-bit data data valid on rising edge of sclk figure 16. cs4340 format 0 (i 2 s) lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode left justified, up to 24-bit data int sclk = 64 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 left justified, up to 24-bit data data valid on rising edge of sclk figure 17. cs4340 format 1
cs4340 20 ds297pp3 lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel internal sclk mode external sclk mode right justified, 24-bit data int sclk = 64 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 24-bit data data valid on rising edge of sclk sclk must have at least 48 cycles per lrck period figure 18. cs4340 format 2 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks internal sclk mode external sclk mode right justified, 16-bit data int sclk = 32 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 16-bit data data valid on rising edge of sclk sclk must have at least 32 cycles per lrck period figure 19. cs4340 format 3
cs4340 ds297pp3 21 7. analog performance plots the following cs4340 analog performance plots were taken from the cdb4340 evaluation board using the audio precision dual domain system two cascade. all base rate mode (brm) plots were taken at a 48 khz sample rate with a 20 hz to 20 khz bandwidth using a 20 khz low-pass brick- wall filter in the dsp analyzer. all high rate mode (hrm) plots were taken at a 96 khz sample rate with a 20 hz to 40 khz bandwith using a 40 khz brickwall filter in the dsp analyzer. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 20. de-emphasis curve
cs4340 22 ds297pp3 -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz figure 21. fft 0 db input, brm, va = 3v figure 22. fft -60 db input, brm, va = 3v -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz -10 +20 -8 -6 -4 -2 +0 +2 +4 +6 +8 +10 +12 +14 +16 +18 d b r a -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs figure 23. fft idle noise, brm, va = 3v figure 24. fade-to-noise linearity, brm, va = 3v -105 -85 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 d b r a -60 +0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 dbfs -105 -85 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 25. thdn vs ampl, brm, va = 3v figure 26. thdn vs freq, brm, va = 3v
cs4340 ds297pp3 23 -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz figure 27. fft 0 db input, brm, va = 5v figure 28. fft -60 db input, brm, va = 5v -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz -10 +20 -8 -6 -4 -2 +0 +2 +4 +6 +8 +10 +12 +14 +16 +18 d b r a -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs figure 29. fft idle noise, brm, va = 5v figure 30. fade-to-noise linearity, brm, va = 5v -105 -85 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 d b r a -60 +0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 dbfs -105 -85 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 31. thdn vs ampl, brm, va = 5v figure 32. thdn vs freq, brm, va = 5v
cs4340 24 ds297pp3 -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 5k 40k 10k 15k 20k 25k 30k 35k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 5k 40k 10k 15k 20k 25k 30k 35k hz figure 33. fft 0 db input, hrm, va = 3v figure 34. fft -60 db input, hrm, va = 3v -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 5k 40k 10k 15k 20k 25k 30k 35k hz -10 +20 -8 -6 -4 -2 +0 +2 +4 +6 +8 +10 +12 +14 +16 +18 d b r a -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs figure 35. fft idle noise, hrm, va = 3v figure 36. fade-to-noise linearity, hrm, va = 3v -105 -85 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 d b r a -60 +0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 dbfs -105 -85 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 d b r a 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz figure 37. thdn vs ampl, hrm, va = 3v figure 38. thdn vs freq, hrm, va = 3v
cs4340 ds297pp3 25 -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 5k 40k 10k 15k 20k 25k 30k 35k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 5k 40k 10k 15k 20k 25k 30k 35k hz figure 39. fft 0 db input, hrm, va = 5v figure 40. fft -60 db input, hrm, va = 5v -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 5k 40k 10k 15k 20k 25k 30k 35k hz -10 +20 -8 -6 -4 -2 +0 +2 +4 +6 +8 +10 +12 +14 +16 +18 d b r a -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs figure 41. fft idle noise, hrm, va = 5v figure 42. fade-to-noise linearity, hrm, va = 5v -105 -85 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 d b r a -60 +0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 dbfs -105 -85 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -94 -93 -92 -91 -90 -89 -88 -87 -86 d b r a 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz figure 43. thdn vs ampl, hrm, va = 5v figure 44. thdn vs freq, hrm, va = 5v
cs4340 26 ds297pp3 8. parameter definitions total harmonic distortion + noise (thd+n) a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converters output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 9. references 1) "how to achieve optimum performance from delta-sigma a/d & d/a converters" by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2) cdb4340 evaluation board datasheet
cs4340 ds297pp3 27 10. package dimensions inches millimeters dim min nom max min nom max a 0.053 0.064 0.069 1.35 1.63 1.75 a1 0.004 0.006 0.010 0.10 0.15 0.25 b 0.013 0.016 0.020 0.33 0.41 0.51 c 0.0075 0.008 0.010 0.19 0.20 0.25 d 0.386 0.390 0.394 9.80 9.91 10.00 e 0.150 0.154 0.157 3.80 3.90 4.00 e 0.040 0.050 0.060 1.02 1.27 1.52 h 0.228 0.236 0.244 5.80 6.0 6.20 l 0.016 0.025 0.050 0.40 0.64 1.27 0 4 8 0 4 8 jedec #: ms-012 controling dimension is millimeters e 16l soic (150 mil body) package drawing d h e b a1 a c l seating plane 1

▲Up To Search▲

Price & Availability of CS4340-BS

	To Download CS4340-BS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .